SOI voltage-tolerant body-coupled pass transistor

ABSTRACT

A method and device for A pass transistor device which includes a source; a drain opposite the source, a body between the source and the drain, and a circuit control network connected between the drain and the source, wherein the circuit control network controls a potential voltage of the body and provides overvoltage protection to the pass transistor.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention generally relates to transistor devices which havea dynamic threshold and more particularly to a dynamic threshold devicewhich has increased current capabilities.

[0003] 2. Description of the Related Art

[0004] Silicon-On-Insulator (SOI) technology, which is becoming ofincreasing importance in the field of integrated circuits, deals withthe formation of transistors in a relatively thin layer of semiconductormaterial overlying a layer of insulating material. Devices formed on SOIoffer many advantages over their bulk counterparts, including: higherperformance, absence of latch-up, higher packing density, low voltageapplications, etc. However, SOI circuits, like other electroniccircuits, are: First, susceptible to electrostatic discharge (ESD), asurge in voltage (negative or positive) that occurs when a large amountof current is applied to the circuit; and second, in need of providingan ideality (a constant voltage swing of 60 mV/decade over severaldecades of current) for analog applications, such as inphase-locked-loop circuits, voltage regulators, and band gap referencecircuits.

[0005] For ESD applications, to discharge ESD impulses, ESD protectionschemes need a low voltage turn-on and a high current drive (the abilityto generate or sink a large amount of current before a large amount ofnegative or positive voltage is developed). Traditional bulk overvoltageprotection schemes, such as diode circuits, do not work well on SOIbecause of the presence of the SOI buried oxide. That is, conventionaldiodes on SOI have small current drivability because the current iscarried laterally and is limited by the thickness of the semiconductormaterial. Thus, developing a new approach or a new type of diode wasnecessary for adequate ESD protection for SOI circuits.

[0006] ESD robustness is important for SOI driver (buffer) and receivercircuits. Receiver circuits, pass transistors, test transistors,feedback keeper elements and other auxiliary transistors on input pinsmust be overvoltage tolerant to protect from ESD events, electricaloverstress, and other high current and voltage conditions. Hence, robustelements are needed to provide ESD robust SOI receiver circuits.Input/output (I/O) networks and off-chip drivers must also provide ESDrobust pull-up and pull down elements. Hence, n-channel or p-channel SOItransistors, used as both pull-up or pull-down elements must provideover-shoot and undershoot protection, electrical overstress protectionand ESD protection.

[0007] An I/O circuit is very susceptible to gate overstress,overvoltage and electrostatic discharge/electrical overstress events.The pass transistor, typically used in receiver networks, bi-directionalcircuits and other applications is extremely useful in protectingagainst overvoltage and electrostatic discharge events.

[0008] For overvoltage events, there are both positive and negativeovershoot concerns that are typically addressed for receiver networks.For ESD events, there are both positive and negative events that occuron both the source and drain of the pass transistor (input or outputside). Human body model (HBM) and machine model (MM) events occur on thepad side of the structure. Charged device model (CDM) events can occuron the receiver side. In all cases, voltage across the pass transistorthat allows it to undergo secondary breakdown is a concern. In SOItechnologies, there is also a concern that the diode is not formedrelative to the bulk substrate. This prevents the operation of diodeaction relative to the bulk for negative undershoot or negative mode ESDphenomenon.

SUMMARY OF THE INVENTION

[0009] In one aspect, the invention provides a structure, method andapparatus which uses a body-limiting network in an ESD device on SOIchips. The invention uses a body-charging network to produce a morerobust ESD. The invention uses an SOI body-augmenting network whichmodulates an SOI body potential and provides a more robust ESD network.The invention provides RC discrimination and a body-limiting network inan ESD network on an SOI chip. The invention also provides RCdiscrimination and body-charging networks in an ESD network.

[0010] The invention includes RC discrimination and a SOI-body augmentednetwork in an ESD network. The invention provides a RCdiscrimination-body controller, a body-modulation network, a SOIbody-augmenting network, and a body-charging network, all for ahalf-pass transistor.

[0011] Thus, the invention provides a structure and method for a passtransistor device which includes a source, a drain opposite the source,a body between the source and the drain, and a circuit control networkconnected between the drain and the source (the circuit control networkcontrols a potential voltage of the body and provides overvoltageprotection to the pass transistor). The circuit control network includesa body-charging element. The body-charging element includes a Lubistor,a body- and gate-coupled silicon over insulator (SOI) diode element, atleast one Lubistor, a silicon over insulator (SOI) metal oxide siliconfield effect transistor (MOSFET), and a body- and gate-coupled siliconover insulator (SOI) metal oxide silicon field effect transistor(MOSFET) diode. The circuit control network includes a body-limitingelement and a voltage divider network. The voltage divider includes atleast one resistor. The resistor includes a buried resistor element anda silicon over insulator (SOI) metal oxide silicon field effecttransistor (MOSFET). The circuit control network includes at least oneresistor-capacitor series configured element whose center node isconnected to the SOI body of the pass transistor.

[0012] Another embodiment of the invention is a silicon over insulator(SOI) metal oxide silicon field effect transistor (MOSFET) device whichincludes a body, a gate opposite the body, a resistive/capacitordiscriminator connected to the gate, and a circuit control networkconnected to the body (wherein a potential voltage of the body ismodulated by the control circuit network to provide electrostaticdischarge (ESD) protection). The control circuit is connected to thegate, modulates the potential voltage of the body, and limits the bodyto a reference voltage. The control circuit includes at least one SOIMOSFET, at least one ESD SO diode, at least one body/gate-coupled SOIdiode, and n-channel and p-channel SOI MOSFETs, at least two RCdiscriminators and at least one control circuit network. The devicefurther includes an input pad connected to the gate, a drain adjacentthe gate, and a source opposite the drain (wherein the control networkis connected to the input pad and the drain and the source is connectedto Vss).

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of preferredembodiments of the invention with reference to the drawings, in which:

[0014]FIG. 1 is a schematic diagram of a body-coupled gated diode;

[0015]FIG. 2 is a graph of the measured characteristics of the voltagevs. the current in the structure shown in FIG. 1;

[0016]FIG. 3 is a graph of the characteristics of the threshold voltagevs. the body bias of the structure shown in FIG. 1;

[0017]FIG. 4 is schematic diagram of a first network using NFETimplementation;

[0018]FIG. 5 is schematic diagram of a first network using PFETimplementation;

[0019]FIG. 6 is a schematic diagram of a PFET/NFET switch with bodylimiting devices and RC coupling of the gate;

[0020]FIG. 7 is a schematic diagram of a body limiter with a resistivedivider and gate RC coupling;

[0021]FIG. 8 is a schematic diagram of a body limiter with a resistivedivider;

[0022]FIG. 9 is a schematic diagram of a resistive divider usingpolysilicon SOI diodes;

[0023]FIG. 10 is a schematic diagram of a resistive divider usingdynamic threshold SOI MOSFETs;

[0024]FIG. 11 is a schematic diagram of a body charging device with abody charging element;

[0025]FIG. 12 is a schematic diagram of a body charging device with aB/G-C DTMOS body charging element;

[0026]FIG. 13 is a schematic diagram of a body charging with an NFET andPFET clamp network;

[0027]FIG. 14 is a schematic diagram of a body limiter;

[0028]FIG. 15 is a schematic diagram of first embodiment of an RCcoupled body pass transistor (half-pass);

[0029]FIG. 16 is a schematic diagram of second embodiment of an RCcoupled body pass transistor;

[0030]FIG. 17 is a schematic diagram of an alternative to FIG. 16;

[0031]FIG. 18 is a schematic diagram of an alternative to FIG. 16 usingNFET implementation;

[0032]FIG. 19 is a schematic diagram of an alternative to FIG. 16 usingPFET implementation;

[0033]FIG. 20 is a schematic diagram of an alternative to FIGS. 18 and19 using PFET and NFET implementation;

[0034]FIG. 21 is a schematic diagram of a first embodiment of apolysilicon gate diode-referenced body pass transistor;

[0035]FIG. 22 is a schematic diagram of a second embodiment of apolysilicon gate diode-referenced body pass transistor;

[0036]FIG. 23 is a schematic diagram of a B/G-C diode reference passtransistor; and

[0037]FIG. 24 is a schematic diagram of a B/G-C diode voltagedivided-pass transistor.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0038] As mentioned above, ESD protection is becoming increasinglyimportant in current technologies. Convention ESD protection devices canbe destroyed if there are forced to accept excessive current. Theinvention described below allows an improved ESD robust network.

[0039] One approach to solving the aforementioned problems, mentioned inU.S. Pat. No. 5,811,857 to Assaderaghi et al. (hereinafter Assaderaghi)which is incorporated herein by reference, discloses a body-coupledgated (B/G-C) diode formed from an (SOI) field-effect transistor (FET).In this structure, the body, gate and drain of the SOI FET are tiedtogether, forming the first terminal of the B/G-C diode. The source ofthe SOI FET forms the second terminal of the B/G-C diode. Both NFETs andPFETs may be used to create the forward-biased operation of the B/G-Cdiode.

[0040] However, the device disclosed in Assaderaghi is limited tooperating in a diodic mode. Assaderaghi is an example of application ofa dynamic threshold technique applied to an SOI MOSFET and configures ina diode-configuration. To the contrary, the invention utilizesbody-coupled devices in a wide variety of circuit structures.

[0041] One configuration of a B/G-C diode is shown in FIG. 1. Morespecifically, FIG. 1 illustrates an NFET B/G-C diode 10 that is formedfrom an SOI MOSFET 30 having an isolation region 24, buried oxide 12,and silicon substrate 14. Two N+ regions are formed, a source region 16and a drain region 17, on a P-type body region 18. A gate electrode 22overlies a gate insulator 21 and defines the gate of the MOSFET 30. Asurface channel 23 lies below gate insulator 21 and on the surface ofthe P-type region 18, wherein the P-type region is also known as thechannel. The source 36, drain 34, body 38 and gate 32 terminals areaffixed to the source region 16, drain region 17, body node region 18and gate electrode 22, respectively. Terminal A, coupled to the body 38,drain 34, and gate 32 terminals, and terminal B, coupled to the sourceterminal 36, form the input and output of an N+/P type B/G-C diode 10.Although not shown, the connections of the terminals can be easily doneat any of the metal layers of MOSFET 30.

[0042] The operation of the MOSFET B/G-C diode shown in FIG. 1 takesplace in two current regions, as illustrated in greater detail in FIG.2. In the first current region, the B/G-C diode provides ideal diodecharacteristics. In the second current region the B/G-C diode providesESD protection. In general, the first current region of the B/G-C diodecorresponds to the functional voltage range from approximately 0 voltsto approximately Vdd, wherein Vdd is the power supply voltage. Theexponential portion of diode characteristics, though, is typicallylimited to zero to approximately +/−0.7 volts because of external andparasitic series resistances. The second current region of the B/G-Cdiode corresponds to the range approximately below zero and above thepower supply voltage, Vdd.

[0043] For the second current region, ESD protection is provided undertwo turn-on conditions of the MOSFET B/G-C diode. The first turn-oncondition occurs when the voltage of the body 38 exceeds the voltage ofthe source 36. When this condition occurs, a forward-biased diodeattribute allows a current flow from the body terminal to the sourceterminal.

[0044] The second turn-on condition occurs when the voltage at the gate32 exceeds the threshold voltage. That is, as the signal pad voltageincreases, the body voltage and the gate voltage will also increase.When the body voltage increases, the threshold voltage decreases. Thus,when the gate voltage exceeds the threshold voltage, current will flowfrom the drain terminal to the source terminal.

[0045] Thus, for the NFET B/G-C diode 10 (FIG. 1), when a positive pulseis applied to the terminal of the NFET (terminal A), the current isdischarged through the P-N diode formed by the body 18 and source 16 ofthe NFET structure. In parallel, as the body voltage increases, thethreshold voltage of the MOSFET 30 decreases, creating a dynamicthreshold and ideal diode characteristics. As the threshold voltage ofthe NFET decreases, the gate-coupling of the NFET turns on the NFET inparallel with the diode. A unique aspect of the B/G-C diode is theparallel operation of diode characteristic of the diode and the body andgate coupled MOSFET interaction. The B/G-C diode uses body-coupling tolower the absolute value of the threshold voltage and gate-coupling toturn on the ESD MOSFET element prior to NFET snapback.

[0046] Likewise, for a PFET B/G-C diode which is also illustrated anddiscussed in Assaderaghi, when a negative pulse is applied to theterminal of the PFET (terminal A), the current is discharged through theN-P diode formed by the body and drain of the PFET structure. Inparallel, as the body voltage decreases, the magnitude of the thresholdvoltage of the PFET decreases, again creating a dynamic threshold andideal diode characteristics. As the threshold voltage of the PFETdecreases, the gate-coupling of the PFET turns on the PFET in parallelwith the diode.

[0047] A distinguishing aspect of the B/G-C diode as compared to otherdiodes is the parallel operation of diodic characteristic of the diodeand the body 25 and gate coupled MOSFET interaction. That is, the B/G-Cdiode uses body-coupling to lower the absolute value of the thresholdvoltage and gate-coupling to turn on the ESD MOSFET element prior to FETsnapback.

[0048]FIG. 2 illustrates the operation of the NMOSFET B/G-C diode 10(lines 52 and 56) compared to the operation of a non-B/G-C diode (lines54 and 58). On the left vertical axis of the graph is a log scale of thecurrent at the first current region (pertaining to lines 52 and 54),indicating the subthreshold regions of MOSFET 30 (line 52) and the FETof the non-B/G-C diode (line 54). The other vertical axis of the graphillustrates the linear scale of the current at the second current region(pertaining to lines 56 and 58), indicating the ESD operational mode ofMOSFET 30 (line 56) and the FET of the non-B/G-C diode (line 58).

[0049] At the first current region, the B/G-C diode (line 52), unlikethe non-B/G-C diode (line 54), attains an ideal subthreshold swing of 60mV/decade. This identity is possible through the coupling of the body tothe gate of MOSFET 30. That is, the gate voltage is directly applied tothe body instead of being capacitively coupled, as with the conventionalnon-B/G-C diode.

[0050] The B/G-C diode, with an identity factor of 1, produces a 60mV/decade slope (line 52), and the non-B/G-C diode, with an identityfactor of approximately 1.45, produces a slope of around 87 mV/decade(line 54). As aforementioned, a 60 mV/decade slope is important inanalog applications for functions such as voltage reference,phase-locked-loop, and voltage regulators.

[0051] At the second current region (lines 56 and 58), the ESDprotection provided by the non-B/G-C (line 58) diode is minimal, quicklybeing dominated by series resistance 59, where the voltage begins toincrement proportionally to the current. The ESD protection provided bythe B/G-C diode is much greater (line 56). The B/G-C MOSFET at thispoint may be conceptually treated as a bipolar device with large (andsometimes infinite) current gain. The drain current can be modeled asthe collector current, and the body (gate) current as the base current.Even though for ease of analysis this device may be treated as a bipolardevice, it is indeed a MOSFET since the current conduction is throughthe surface channel and is controlled by the gate. The “apparent” gainof the “bipolar” device is large, because the threshold voltage (Vt) ofthe MOSFET is being modulated by the applied bias to the silicon film.This gives the appearance of large bipolar gain at low biases.

[0052]FIG. 3 demonstrates the modulation of the threshold voltage by theapplied body bias. The modulation of two devices is depicted. One of thedevices has a shorter channel length than the other. Line 61 illustrateswhen L_(drawn), the drawn dimensions of the channel length, is equal to0.25 μn, and line 62 illustrates when L_(drawn) is equal to 0.20 μn.Thus, the B/G-C diode uses body-coupling to lower the absolute value ofthe threshold voltage and create a dynamic threshold. Consequently,control of the threshold voltage allows for excellent control of thediode characteristics. Furthermore, by changing Vt-adjust implants(implants that are utilized to control the threshold voltage) of aMOSFET, the I off the B/G-C diode (e.g., Ioff of the MOSFET) can easilybe changed by several orders of magnitude. This change is depicted bymoving line 52 to the left or right, which is not easily accomplished inregular diodes.

[0053] Carrying the bipolar analogy one step further, it becomes clearwhy connecting the collector and base together will form a diode. Here,the gate and the body may form the base terminal, the drain may be thecollector terminal, and the source may be the emitter terminal. Eventhough the base (gate) current might have non-identity, its sum with thecollector current will remain ideal because the collector current isseveral orders of magnitude larger than the base current. As seen, thisdiode will have a much larger current than the conventional diode of thesame size.

[0054] SOI MOSFETS achieve an ESD robustness of less than 1V/μm with thegate floating, and approximately 1V/μm with the gate grounded.Conventional lateral diode elements reach a limit of EDS robustness of5V/μm in 5S, 6.5V/μm in 6S and 11V/μmin 7S. With the body coupled andgate coupled structures described below, the ESD robustness of theinventive MOSFET achieved 1 8.8V/μm. From these results, it is clearthat, with the invention, the robustness of pass transistors can beassisted by body coupling. This improves ESD robustness by augmentingthe action of the diode elements. The inventive elements provide currentbypass to assist in the ESD robustness.

[0055] More specifically, in one embodiment, the inventive structure isa pass transistor, which incorporates networks that bias, couple, andset the body voltage during such overvoltage phenomenon. Anotherembodiment of the invention is a resistor/capacitor (RC) coupled bodypass transistor.

[0056]FIG. 4 illustrates a network according to the invention that usesan NFET implementation. In FIG. 4, a pad 40, a capacitor 41, a passtransistor 43, a resistive transistor 42, and element 44, which limitsthe voltage that the body can rise to and sets the reference voltage,are illustrated. The body 45 of the pass transistor 43 is connected tothe input 40 by the RC network (e.g., resistive transistor (e.g., buriedresistor) 42 and capacitor 41) such that when a pulsed event occurs(e.g., overvoltage, overcurrent), the voltage of the body 45 rises. Thisvoltage rise of the body element 45 lowers the threshold voltage of thepass transistor 43, which causes the pass transistor 43 to turn on. Inthis state, the body 45 is dynamically coupled, thereby allowing ahigher current drive, a lower turn-on voltage and at the same time, lessvoltage stress.

[0057] The structure in FIG. 4 is an NFET implementation of theinvention. FIG. 5 illustrates a PFET implementation, which operates asdescribed above except, capacitor 41 and resistive transistor 42initiate RC coupling of the gate 45. Element 44 acts as a voltagereference which limits the body potential to the reference voltageV_(ref). In an ESD event, the RC network couples the gate 45 of the passtransistor 43.

[0058] Similarly, FIG. 6 illustrates a PFET/NFET switch which includesRC networks 41, 42 which operate as described above. In addition, thestructure in FIG. 6 includes body limiting devices 60 which limit thebody voltage during functional operation. In the example shown in FIG.6, the body limiting devices 60 are coupled to reference voltages ofV_(ref2)=Vdd-(IV_(t)I+0.5V) and V_(refy)=V_(tm)+0.5V. for the RCnetworks. The body limiters 60 can be any devices well known to thoseordinarily skilled in the art (e.g., NFET, PFET, etc.) that are used tolimit voltage or provide a reference voltage.

[0059]FIG. 7 illustrates a similar structure; however, the resistivetransistor 42 is replaced with a conventional resistor 71. As would beknown by one ordinarily skilled in the art given this disclosure, theresistive transistors 42 and resistors 71 can be generally substitutedfor one another in the structure disclosed herein. In thisimplementation, the body voltage is coupled by the two NFET devices 60in series, forming a resistive divider as well as a second parallelcurrent path. When the pad voltage increases, node 45 rises, increasingthe current drive of element 43.

[0060] Similarly, in FIG. 8, the structure includes body limiterelements 60. However, in the structure shown in FIG. 8, the gates 70 ofthe body limiter elements 60 are connected to the voltage source Vss orto a reference voltage. This separates the gates from the pad input nodeand allows setting the reference values of the elements 60.

[0061]FIG. 9 illustrates a similar structure; however, the body limiterelements comprise lateral unidirectional bipolar transistors 90 (knownas Lubistors). Lubistor elements have been shown to provide higher ESDrobustness compared to MOSFET structures. The Lubistors cause node 45 toprovide body modulation and increased current drive for element 43 aswell as to provide an alternative current path.

[0062]FIG. 10 again shows a similar structure; however, the body limiterelements are replaced with dynamic threshold SOI MOSFETs 100. Dynamicthreshold B/G-C diodes have lower turn-on voltage than Lubistors. In asimilar manner, FIG. 11 illustrates a transistor 110 (e.g., body limiterelement) which has its gate 111 connected to the gate 112 of the passtransistor element 43. As the gate 112 rises, the gate of element 111rises, turning on element 110. This charges the body of element 43,providing increased current drive.

[0063]FIG. 12 illustrates a similar structure having body andgate-coupled dynamic threshold device 120 as the body charging elements.In this case, both the gate and body of element 120 rises, having anincreased body charging and higher current drive. This causes node 45 torise faster than the circuit in FIG. 11.

[0064]FIG. 13 illustrates a clamp network having pass transistors 43, apad 40 and body charging elements 130 which function in a similar manneras discussed above. As the pad rises, the gate of element 130 rises,causing the element 130 to turn on, charging the body of element 43. Fornegative pulses, the PFET 130 turns on, causing the element 43 to groundto have its body rise.

[0065]FIG. 14 is similar to FIG. 13; however in FIG. 14, the bodylimiter elements 140 are connected directly to the pass transistors 43.In element 40, the body voltages are limited to the reference levels,V_(ref1) and V_(ref2).

[0066]FIG. 15 is an equivalent circuit to that shown in FIG. 4 in thatthe pad 40, capacitor 41, resistor 71 (42) and the pass transistor 43are illustrated. FIG. 15 also shows the receiver 150. This equivalentcircuit is provided to more clearly explain the embodiment of theinvention shown in FIG. 16 which is a resistor-divider referenced bodypass transistor.

[0067] In FIG. 16, the pass transistor 43 is connected between the pad40 and the receiver 150. A first resistor 160 is placed between the pad40 and the body element 45. The first resistor 160 is connected betweenthe body 45 and the drain side 162 of the pass transistor 43. A secondresistor 161 is placed between the body element 45 and the source side163 of the pass transistor 43.

[0068] As the voltage rises on the pad node 40, the body 45 voltagerises with the pad 40. When the body 45 voltage rises, the thresholdvoltage of the pass transistor 43 is reduced, reducing the voltage dropacross the pass transistor 43. Secondly, the two resistors 160, 161 actas a divider to limit or set the body 45 voltage relative to the pad 40to reduce voltage stress. At high current, the parallel elements 160,161 will also provide a second current path to further increase therobustness of the pass transistor element 43.

[0069] In an alternative embodiment, the two resistor elements 160, 161can be two MOSFETs 170, 171, 180, 181 as shown in FIGS. 17 and 18. Thegates of the MOSFETs, can be activated by an external pulse, or beturned on by a reference voltage or connected to Vdd. The two MOSFETscan be p-channel or n-channel or one of both. In all cases, thebody-biasing network sets the body so that the voltage is defined on thebody and rises with the input node. In all cases, the two elements limitthe maximum voltage across the pass transistor as well as provide analternative current path. In FIGS. 17 and 19, these can be independentlybiased whereas FIG. 18 is activated by gate 182 potential. FIG. 20 isequivalent to FIG. 19 and illustrates that conventional resistors R₁, R₂can be used or resistive NFET and PFET transistors 200, 201 can besubstituted into the circuit to achieve the same result.

[0070] Yet another embodiment of the invention is a polysilicon gateddiode-referenced body pass transistor, as shown in FIG. 21. In SOI,lateral diode elements are constructed using a P+ anode, a gate, and anN+ cathode. By using two diodes or more in a series configuration, thevoltage level of a pass transistor element can be set for body-biasingand reduced voltage stress. In the embodiment shown in FIG. 21, the passtransistor 43 is between the pad 40 and the receiver 150, and at leastone diode 210 is used in parallel with the pass transistor 43.

[0071] The diode 210 is a Lubistor or SOI-gated diode and is positionedbetween the drain 211 and the body 45, so that the diode's anode is atthe drain 211 and cathode is at the body 45. As the pad 40 voltagerises, the diode 210 forward biases, increasing the voltage of the body45. This provides more current drive to the pass transistor 43, lowersits Vt above 0.7 V and provides a second current path in series with thepass transistor drain. The pass transistor body-source junction (45,211) can act as a diode in series with the poly-bound diode (Lubistor)element 210 so that, at voltages above 1.4 V, the combination acts astwo diodes in series. Thus, this network effectively provides abody-coupled MOSFET in parallel with a “series diode string” between thepad and the receiver network.

[0072] The structure shown in FIG. 22 is similar to that shown in FIG.21 and includes a second Lubistor or gated diode element 220 connectedto the body 45 and the source 221 of the pass transistor 43. This setsthe body 45 of the pass transistor 43 as the center node of the twodiode elements 210, 220. The body 45 voltage is then set as a referencevoltage between the two diode elements. If current flows through thecircuit shown in FIG. 22, the center point voltage 43 can be set by thebody series resistance as well as the forward voltage potentials. Thus,this circuit produces body coupling of the pass transistor 43 forreduced voltage stress, increased current drive and improved delay, aswell as an alternative current path to enhance the pass transistor ESDrobustness. In this embodiment, the number of diodes can be varied tomake this dynamic threshold metal oxide semiconductor (DTMOS) conceptsuitable for SOI networks between 1.5 V Vdd and below.

[0073] Another embodiment of the invention is a body/gate coupled diodereference body pass transistor, as shown in FIG. 23. In this embodiment,the element for the “diode reference” circuit is a body-and gate-coupledMOSFET 230 whose gate, body and drain are connected. The B/G-C diodeelement is placed between the body 45 and the drain 211 of the passtransistor element 43. As in the prior embodiment, a second B/G-C diodeelement 230 is placed in parallel with the body 45 and source 221 of thepass transistor 43. The B/G-C reference network is then used to set thebody 45 voltage of the pass transistor 45, which again provides theenhanced current drive and improves the delay of the pass transistor.This establishes a more voltage tolerant network, and provides a secondcurrent path to avoid pass transistor failure. As shown in FIG. 24,there can be more than one B/G-C element (e.g., 230, 240). Body- andgate-coupled elements have demonstrated a higher ESD robustness andlower turn-on voltage compared to Lubistor elements.

[0074] In charged device model (CDM) events, the current of the ESDpulse comes from inside the chip and looks for any path to get to thegrounded pad. The current either comes from Vdd, Vss, or elementscontained in the receiver circuit. In all of the cases, the passtransistor is typically an element in the path of failure. Hence, forCDM events, the identical issue is present but the elements (MOSFETs,references, diodes, B/G-C elements, resistors) role is reversed wherethe current is coming from the source instead of from the pad's side onthe drain. The invention provides a new family of pass transistor logiccircuits that are voltage tolerant and robust pass transistors in SOIand have performance delay advantages, current drive advantages andother functional concerns. These embodiments do not preclude addition ofother elements for voltage tolerant gates which could be used inconjunction with these pass transistor elements, as would be known toone ordinarily skilled in the art given this disclosure.

[0075] While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

What is claimed is:
 1. A pass transistor device comprising: a source; adrain opposite said source; a body between said source and said drain;and a circuit control network connected between said drain and saidsource, said circuit control network controlling a potential voltage ofsaid body and providing overvoltage protection to said pass transistor.2. The device in claim 1, wherein said circuit control network comprisesa body-charging element.
 3. The device in claim 2, wherein saidbody-charging element comprises a Lubistor.
 4. The device in claim 2,wherein said body-charging element comprises a body- and gate-coupledsilicon over insulator (SOI) diode element.
 5. The device in claim 2,wherein said body-charging element comprises at least one Lubistor. 6.The device in claim 2, wherein said body-charging element comprises asilicon over insulator (SOI) metal oxide silicon field effect transistor(MOSFET).
 7. The device in claim 2, wherein said body-charging elementcomprises a body- and gate-coupled silicon over insulator (SOI) metaloxide silicon field effect transistor (MOSFET) diode.
 8. The device inclaim 1, wherein said circuit control network comprises a body-limitingelement.
 9. The device in claim 1, wherein said circuit control networkcomprises a voltage divider network.
 10. The device in claim 9, whereinsaid voltage divider includes at least one resistor.
 11. The device inclaim 10, wherein said resistor comprises a buried resistor element. 12.The device in claim 10, wherein the resistor comprises a silicon overinsulator (SOI) metal oxide silicon field effect transistor (MOSFET).13. The device in claim 1, wherein said circuit control networkcomprises at least one resistor-capacitor series configured elementwhose center node is connected to said SOI body of said pass transistor.14. A silicon over insulator (SOI) metal oxide silicon field effecttransistor (MOSFET) device comprising: a body; a gate opposite saidbody; a resistive/capacitor discriminator connected to said gate; and acircuit control network connected to said body, said circuit controlnetwork modulating a potential voltage of said body to provideelectrostatic discharge (ESD) protection.
 15. The device in claim 14,wherein said control circuit is connected to said gate.
 16. The devicein claim 14, wherein said control network circuit modulates saidpotential voltage of said body.
 17. The device in claim 14, wherein saidcontrol network circuit limits said body to a reference voltage.
 18. Thedevice in claim 14, wherein said control circuit comprises at least oneSOI MOSFET.
 19. The device in claim 14, wherein said control networkcomprises at least one ESD SOI diode.
 20. The device in claim 14,wherein said control network circuit comprises at least onebody/gate-coupled SOI diode.
 21. The device in claim 14, wherein saidcontrol network comprises n-channel and p-channel SOI MOSFETs, at leasttwo RC discriminators and at least one control circuit network.
 22. Thedevice in claim 14, further comprising: an input pad connected to saidgate; a drain adjacent said gate: and a source opposite said drain,wherein said control network is connected to said input pad and saiddrain and said source is connected to Vss.